Risc V
Showing 14 of 14 projects
An open-source, community-driven real-time operating system (RTOS) designed for resource-constrained IoT devices.
A secure embedded operating system for microcontrollers that runs multiple concurrent, mutually distrustful applications on Cortex-M and RISC-V platforms.
An open-source microcontroller operating system designed for energy-efficient, real-time IoT devices with a small memory footprint.
A high-performance C++ library for Unicode validation and transcoding (UTF-8/16/32, Latin1, Base64) using SIMD instructions.
A Rust-based downstream fork of coreboot, designed as a modern firmware implementation for booting LinuxBoot payloads.
A public permissionless layer-1 blockchain that serves as a universal verification layer for the Nervos network.
A lightweight, cloud-native operating system kernel written in Rust with Linux binary compatibility, designed for serverless and containerized workloads.
A language for formally specifying instruction-set architecture (ISA) semantics with tooling for emulators, documentation, and verification.
A GitHub Action that executes jobs on non-x86 CPU architectures (ARM, s390x, ppc64le, RISC-V) via QEMU emulation.
An open-source framework for building hardware-enforced trusted execution environments (TEEs) on RISC-V processors.
A formal and executable RISC-V ISA specification written in F# with a purely functional style, designed for clarity and reference.
Ada and SPARK drivers library for bare-metal microcontrollers, supporting ARM Cortex-M and RISC-V platforms.
A formal specification of the RISC-V instruction set architectures (RV32I, RV64I) and extensions (A, M) written in the Coq proof assistant.
GNAT Ada Run Time Systems based on FreeRTOS for Cortex-M microcontrollers, supporting boards like Arduino Due and BBC micro:bit.
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