Question 1

How to use riscv-coq to verify a RISC-V processor design?

Accepted Answer

Integrate riscv-coq as a Coq library in your project, then write Coq proofs that your hardware model's semantics match the specification. This requires expertise in Coq and possibly additional tools for modeling hardware in a formal language.

Question 2

What's the difference between riscv-coq and the official RISC-V Sail model?

Accepted Answer

riscv-coq is a Coq-based specification auto-generated from Haskell, focused on machine-checked proofs within Coq's ecosystem, while Sail is a domain-specific language used by RISC-V International for ISA specification, often targeting simulation and validation rather than formal verification.

Question 3

Does riscv-coq support RISC-V floating-point instructions?

Accepted Answer

No, riscv-coq currently only supports the A and M extensions, so floating-point instructions (F and D extensions) are not included. You would need to extend the specification manually or use alternative tools.

Question 4

How to fix build errors when compiling riscv-coq?

Accepted Answer

Follow the troubleshooting tip in the README: check the bedrock2 project's continuous integration for a working version, as it uses riscv-coq as a dependency. Ensure you have the latest Coq and coqutil installed correctly.

Question 5

Can riscv-coq be integrated with other verification tools like Verilog?

Accepted Answer

It's possible but non-trivial; riscv-coq is a Coq library, so integration would require bridging frameworks or custom tools to link Coq proofs with Verilog descriptions, such as through co-simulation or formal equivalence checking.

Question 6

Is riscv-coq actively maintained and up-to-date with RISC-V specs?

Accepted Answer

The project is maintained by MIT PLV and used in research like bedrock2, but it may not keep pace with the latest RISC-V specifications; check the GitHub repository for recent commits and issues to gauge activity.

RISC-V Specification in Coq

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