A language for formally specifying instruction-set architecture (ISA) semantics with tooling for emulators, documentation, and verification.
Sail is a domain-specific language for formally specifying the semantics of processor instruction-set architectures (ISAs). It enables architects and verification engineers to write precise, machine-checkable definitions of how instructions behave, which can then be used to generate emulators, documentation, and verification models. The language solves the problem of maintaining consistency between informal pseudocode and various downstream tools.
ISA architects, hardware verification engineers, and researchers working on formal methods for processor design. It's particularly valuable for teams developing or verifying complex ISAs like Arm, RISC-V, or CHERI extensions.
Sail provides a single authoritative source for ISA semantics that can be automatically transformed into multiple artifacts (emulators, documentation, verification models), eliminating inconsistencies between different representations. Its lightweight dependent typing and integration with theorem provers enable rigorous verification while maintaining engineer-friendly syntax.
Sail architecture definition language
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Automatically checks bitvector lengths and type consistency using the Z3 SMT solver, reducing human error in ISA definitions as highlighted in the README.
From a single specification, produces emulators (C/OCaml), documentation (LaTeX/AsciiDoc), and verification models, ensuring consistency across tools like concurrency analysis and theorem proving.
Used by the RISC-V Foundation and for Arm specifications (e.g., Armv9-A and Morello), demonstrating real-world reliability and applicability in major projects.
Exports to Coq, Isabelle, or HOL4 for formal verification, enabling rigorous security proofs as evidenced by the Arm Morello ISA proofs referenced in the README.
The README explicitly states 'Not all of these are currently supported for all models', leading to inconsistency and requiring users to verify status for their specific ISA.
Installation via opam and integration with tools like Z3, theorem provers, and memory model analyzers adds significant setup complexity, especially for newcomers to formal methods.
Some models (e.g., x86 and IBM POWER) are in older Sail versions, indicating maintenance challenges and lack of uniform updates across the ecosystem.