How to port VerilogBoy to a different FPGA board?

Porting is non-trivial; you need to modify the top-level HDL and constraints in the target directory, but the project currently only has a Pano G1 port with complex memory controller dependencies. Start by studying the existing port and adapting it for your board's resources.

VerilogBoy or Mister FPGA for Game Boy emulation?

VerilogBoy is a custom RTL implementation focused on education and modification, while Mister uses polished, pre-built cores. Choose VerilogBoy for learning hardware design, but Mister for a more stable and feature-rich gaming experience.

Does VerilogBoy support Game Boy Color games?

No, it only targets monochrome Game Boy models (DMG) as stated in the philosophy, focusing on behaviors common to all GS variants without Color-specific features.

What's the easiest way to test VerilogBoy without an FPGA?

Use the included Verilator-based simulator; install dependencies like SDL2 and run ROMs with commands like './vb_sim --mbc'. It supports headless mode and waveform tracing for debugging.

Why does VerilogBoy fail some PPU tests?

The PPU implementation simplifies the original design by using one pipeline instead of separate BG and sprite pipelines, leading to inaccuracies in timing and interrupt handling as shown in the Mooneye test results.

Can I use VerilogBoy for commercial projects?

The license is mixed: HDL under OHDL, software under MIT, and some parts under LGPL or ISC. You must comply with all licenses, which may require sharing modifications or attributions for derivative works.

Open-Awesome

VerilogBoy

NOASSERTIONVerilog

An open-source Game Boy compatible console implemented in Verilog RTL for FPGA hardware.

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What is VerilogBoy?

VerilogBoy is an open-source hardware implementation of a Nintendo Game Boy compatible console written in Verilog. It provides a complete RTL (Register Transfer Level) design that can be programmed onto FPGA boards to create physical hardware capable of running original Game Boy games. The project implements the Game Boy's SM83 CPU, PPU graphics unit, sound generator, and other core components in hardware description language.

Target Audience

FPGA developers, digital design engineers, and retro computing enthusiasts interested in hardware emulation and Game Boy architecture. It's particularly suited for those wanting to understand or modify Game Boy hardware at the RTL level.

Value Proposition

Unlike software emulators, VerilogBoy runs on actual FPGA hardware, providing a unique hands-on approach to retro gaming preservation and hardware design education. It offers a complete, synthesizable implementation with demonstrated commercial game compatibility.

Overview

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Use Cases

Best For

Learning Game Boy hardware architecture through RTL implementation
Creating FPGA-based Game Boy compatible hardware
Digital logic and Verilog educational projects
Hardware preservation of retro gaming systems
Developing custom Game Boy hardware modifications
Experimenting with hardware emulation on FPGA platforms

Not Ideal For

Projects requiring high accuracy or cycle-accurate Game Boy emulation
Developers looking for a ready-to-use, multi-platform FPGA solution
Teams needing extensive documentation and community support for quick integration
Those wanting a simple, software-based Game Boy emulator without hardware dependencies

Pros & Cons

Pros

Accurate CPU Core

The SM83 CPU implementation passes all Blargg's tests and key Mooneye timing tests, ensuring functional correctness for most game logic.

Comprehensive Simulation Environment

Includes a Verilator-based simulator with SDL support, allowing ROM testing without FPGA hardware and detailed waveform tracing.

Demonstrated Game Compatibility

Successfully runs commercial games like Tobu Tobu Girl on the Pano G1 FPGA, proving real-world usability for retro gaming.

Educational RTL Design

Provides a complete, synthesizable Verilog implementation ideal for learning Game Boy hardware architecture and digital design.

Cons

Limited Platform Support

Currently only targets the Pano Logic G1 FPGA, with no out-of-the-box support for common development boards like DE10-Nano or Arty.

Incomplete PPU Accuracy

The README admits the PPU implementation is 'wrong,' failing multiple timing and interrupt tests due to architectural simplifications like a single fetcher.

Complex Setup Dependencies

Requires multiple tools like Verilator, SDL2, and rgbds, with non-trivial installation steps across different operating systems.

Sparse and Outdated Documentation

Architecture diagrams are marked as outdated, and guidance for porting or advanced customization is minimal, relying on user exploration.

Frequently Asked Questions

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