Vhdl

ghdlVHDL

An open-source analyzer, compiler, simulator, and experimental synthesizer for VHDL, supporting multiple language standards and backends.

fusesocPython

Package manager and build abstraction tool for FPGA/ASIC development, enabling IP core reuse and SoC creation.

awesome-fpga

A curated collection of FPGA resources including tutorials, books, devices, tools, and community references for hardware development.

vscode-verilog-hdl-supportTypeScript

A comprehensive VS Code extension providing syntax highlighting, linting, formatting, and language server support for Verilog, SystemVerilog, VHDL, and related hardware description languages.