Hardware Description Language
3 projects
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ghdlVHDL
An open-source analyzer, compiler, simulator, and experimental synthesizer for VHDL, supporting multiple language standards and backends.
#fpga#hacktoberfest#compiler
Stars2.8k
Forks417
Last commit3 days ago
fusesocPython
Package manager and build abstraction tool for FPGA/ASIC development, enabling IP core reuse and SoC creation.
#ip-core-management#fpga#verilog
Stars1.4k
Forks272
Last commit12 days ago
svlsRust
A language server for SystemVerilog providing linting and IDE integration.
#language-server#verilog#ide-integration
Stars580
Forks32
Last commit2 days ago
Community-curated · Updated weekly · 100% open source
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